1. Field of the Invention
The present invention relates to a radio communication technology, and more specifically, relates to a radio receiver, a radio communication system, a radio communication method, and a program which achieve synchronization in high-speed radio communications.
2. Description of Related Art
Recently, communication rates in information communications have been increasing. Higher communication rates have also been increasingly demanded in radio communications in order to achieve real-time transmission/reception of rich content, such as a moving images and seamless connections to wired communications. In information communications, it is indispensable to synchronize signals between a transmitting side and a receiving side in order to correctly achieve data transmission/reception. However, in radio communications, a clock signal is not transmitted independently on the transmitting side, and a synchronization clock is generated on the receiving side. Thus, phase synchronization between the transmitting side and the receiving side is a challenging task, with the overall performance of a radio communication system depending on the quality of the synchronization.
A known technique for data synchronization in radio communications is to use a known pattern sequence. In this technique, a transmitter transmits a signal of a known pattern sequence to a receiver, the known pattern sequence being arranged in the preamble or the header of a frame. The receiver calculates a correlation between the received signal and a signal of the known pattern sequence or performs an arithmetic operation for pattern matching therebetween, and thereby detects the known pattern sequence in the received signal. In this way, symbol synchronization between the transmitter and the receiver is achieved.
For example, Japanese Patent Application Publication No. 2001-103044 (Patent Literature 1) discloses a symbol synchronization method in which a receiver oversamples a received signal at a rate of N times per symbol, and then calculates a correlation between the oversampled signal and a known symbol sequence. In the symbol synchronization method, a certain sampling point is selected and used as a symbol timing. Specifically, the certain sampling point is a sampling point existing foremost among sampling points which are near a sampling point having the maximum amplitude of a calculated correlation function and which concurrently have amplitudes equal to or higher than a predetermined threshold.
Japanese Patent Application Publication No. 2003-218967 (Patent Literature 2) discloses a timing synchronization method in which a synchronization timing point is obtained by: oversampling a received frame including multiple synchronization symbols; and then by calculating a correlation between the multiple digitized synchronization symbols and a reference symbol for timing synchronization which has been set in advance.
Japanese Patent Application Publication No. 2003-234791 (Patent Literature 3) discloses a detection method of finding a symbol timing by performing an arithmetic operation for a delay detection of an input baseband signal oversampled by N times.
Japanese Patent Application Publication No. 2007-181016 (Patent Literature 4) discloses a configuration of sampling signals at a frequency which is an integer multiple of a symbol modulation rate.
As described above, in each of the synchronization techniques using a known pattern sequence, a signal is sampled at a higher rate than a symbol rate, and then a known pattern sequence is detected from the oversampled data. Normally, as disclosed in the aforementioned Patent Literatures 1 to 4, the signal is oversampled at a rate which is an integer multiple of a symbol rate, more typically at a rate 2N times (N is an integer) as high as the symbol rate. Therefore, the known pattern sequence is formed of an integer number of bits. Thus, whichever technique of the correlation calculation or pattern matching is used, detection is generally difficult unless the oversampling rate is set as an integer multiple to correspond to the integer number of bits.
In a region in which a relatively low symbol rate is used, the oversampling at a rate of an integer multiple, such as 8, 16, 100, or 128 times, can be performed readily even in radio communications. However, in a region in which a data rate exceeding 1 Gbps is used, the bandwidth of the signal and the bandwidth of the circuit are close to each other. Thus oversampling at a rate of an integer multiple is difficult.
As an analog to digital converter (ADC) used for oversampling, even high-end ADC's currently available on the market have a performance of approximately 4 Gsps. Accordingly, when a data rate of 3 Gbps is assumed, a commercially available ADC cannot achieve oversampling at even two times, which is the smallest integer multiple. There do exist ADC's for measuring equipment capable of a performance of up to 50 Gsps, however, from a viewpoint of cost, they are prohibitively expensive for a consumer communication apparatus. In summation, with the increasing rate of data in recent radio communications, the oversampling at an integer multiple of a symbol rate has become difficult, and thus synchronization has become very difficult.
As described above, in the aforementioned conventional techniques disclosed in Patent Literatures 1 to 4, oversampling at an integer multiple is performed in one symbol frequency, and a circuit thereof is configured also based on the integer multiple. In a case where any of the conventional techniques disclosed in Patent Literatures 1 to 4 is applied to achieve radio communications at a data rate of 3 Gbps by using an ADC having a sampling rate of approximately 4 Gsps, there arises a need for an extra conversion process in which upsampling or interpolation is performed before calculating a correlation value, and then a signal having a rate of an integer multiple is generated. This causes an additional error due to the upsampling or the interpolation. In addition, when the correlation calculation or the arithmetic operation of pattern matching is performed, oversampling at a rate of even two times, which is the smallest integer multiple, requires a register two times as long as the known pattern sequence. Consequently, this leads to a largely configured circuit and an increase of power consumption.